ⓘ Une erreur inattendue s'est produite lors du traitement de votre demande.
Veuillez rafraîchir la page et réessayer.
Si le problème persiste, veuillez nous contacter avec votre problème.
Vous pouvez toujours gérer vos préférences et mettre à jour vos intérêts pour vous assurer de recevoir les opportunités les plus pertinentes.
Préparez-vous à découvrir votre prochaine grande opportunité.
SCALINX
, France
Job function SCALINX’s design team is seeking a dynamic and highly motivated Physical design engineer who will participate to the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market. The candidate will execute the backend process through the entire RTL-to-GDSII flow including hierarchical floor planning, place & route,
Source de l'emploi : SCALINXmicroTECH Global Limited
, France
We are searching for a Physical Design / Back-End Technical Leader who will contribute to define, implement and follow-up on the Back-End technical aspects. You will support the definition of new products and in interface activities with customers. Work description Be responsible for the methodology, the design cycle of all physical partitions an
Source de l'emploi : microTECH Global LimitedAxelera AI
Paris, Île-de-France, France
About Us At Axelera.ai , we are a pioneering semiconductor startup company in Europe, dedicated to pushing the boundaries of technology with a focus on multi-core in-memory compute SoCs. As a member of our physical design team, you will play a pivotal role in contributing to our ongoing success and innovation. Location We offer a flexible, hybrid
Source de l'emploi : Axelera AIAxelera AI
Paris, Île-de-France, France
About Us At Axelera.ai , we are a pioneering semiconductor startup company in Europe, dedicated to pushing the boundaries of technology with a focus on multi-core in-memory compute SoCs. As a member of our physical design team, you will play a pivotal role in contributing to our ongoing success and innovation. Location We offer a flexible, hybrid
Source de l'emploi : Axelera AIMACOM
, France
MACOM designs and manufactures semiconductor products for Data Center, Telecommunication and Industrial and Defense applications. Headquartered in Lowell, Massachusetts, MACOM has design centers and sales offices throughout North America, Europe and Asia. MACOM is certified to the ISO9001 international quality standard and ISO14001 environmental ma
Source de l'emploi : MACOMmicroTECH Global Limited
, France
Position: Senior RTL Designer Type of contract: Permanent, Full time Location: Montbonnot (Grenoble area, France) or Sophia Antipolis (Nice area, France) About the role: You will be part of the Hardware CPU team, in charge of the full development of the new generation of high-performance processors in very advanced technology nodes. The company i
Source de l'emploi : microTECH Global LimitedmicroTECH Global Limited
, France
80K EUR per annum plus bonus and benefits Job Description Position: Senior Digital IC Design Engineer Location: Sophia Antipolis, France About the role: You will be involved in the development of next generation IP solutions, enabling the creation of extremely configurable digital circuits. You will be responsible to architect and design the ne
Source de l'emploi : microTECH Global LimitedSecure IC
, France
Permanent contract (CDI), based in Rennes or Paris. Within the Hardware Design team, in the context of customer and Road-map projects, your missions will be as follows: Configure the various Process Design Kits from multiple foundries (TSMC, GF, ST, …) on the workstations; Execute/maintain the logic synthesis flow, the Placement and Routing (PAR) f
Source de l'emploi : Secure ICParis
Senior Physical Design Engineer (W/M)
* Contract Type: Full-time (CDI)
* Location: Paris
* Ref: 1283
* Contact: ******************
Recruiting Company:
French fabless semiconductor manufacturer specialized in the design and marketing of highly integrated, mixed-signal semiconductor products for markets demanding wideband and low power analog-to-digital, digital-to-analog conversion.
Role:
The Design Team is looking for a dynamic and highly motivated Physical design engineer who will participate to the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market.
The candidate will execute the backend process through the entire RTL-to-GDSII flow.
Responsibilities:
* Lead the physical implementation from RTL to GDSII of a complex ASIC in advanced CMOS process (max 22nm).
* Collaborate closely with the RTL design team to comprehend digital architecture and execute physical design.
* Contribute to defining and refining the physical implementation flow.
* Manage floorplan, pin placement, power planning, and block/top-level assembly.
* Contribute to defining the supply strategy and selecting standard cells.
* Develop timing budgets and draft power intent (SDC) based on design information and specifications.
* Ensure timing and physical closure, incorporating lithography optimizations.
* Conduct Quality Assurance checks (DRC, LVS, equivalence, power intent checking).
* Perform Quality of Result checks, including signoff timing and power analyses.
* Integrate DFT scan functionality and contribute to evaluating the fabricated ASIC in the measurement lab.
* Collaborate within a team for the successful design of a state-of-the art ASIC.
* Participate in design reviews and document processes in accordance with company QA policy.
Requirements:
* You hold an MSc or PhD in Electrical Engineering or equivalent, with over 10 years of hands-on experience in physical design of digital IC from RTL to GDSII, and knowledge of scripting languages (TCL/Python/Bash/Make).
* Must have physical design flow experience: Cadence, full RTL to GDS2 execution with 22 nm and below.
* Could haves: large designs, advanced CMOS technologies and high clock speed, physical implementation of digital processing functions for Mixed-Signal ICs such as A/D Converters, D/A Converters, and/or RF transceivers.
* You demonstrate analytical and problem-solving skills, are a team player with a critical attitude and sense of initiative, communicate fluently in oral and written English.
Education:
BAC+5, Master's Degree, Engineering School
RHESO.TECH, a specialized recruitment agency
https://www.rheso.tech/
Key words: Design, CMOS, ASIC, RTL, DGSII, Cadence, Converter, Transceiver, DFT
Senior physical design engineer (W/M) emplois en Paris
ⓘ Une erreur inattendue s'est produite lors du traitement de votre demande.
Veuillez rafraîchir la page et réessayer.
Si le problème persiste, veuillez nous contacter avec votre problème.
Vous pouvez toujours gérer vos préférences et mettre à jour vos intérêts pour vous assurer de recevoir les opportunités les plus pertinentes.
Préparez-vous à découvrir votre prochaine grande opportunité.